U.S. Pat. Nos. 5,841,696 and 5,867,430 to Chen et al. describe non-volatile flash memory devices that enable simultaneous read and write operations. The disclosed memory may be organized into at least two banks, each bank including a number of sectors. Each bank shares the X decode logic (including sector decode and wordline decode logic for all banks), but has its own Y decode logic. A plurality of latches are provided which are connected to memory access lines. Virtually simultaneous operations are achieved by time multiplexing the X decode path between read and write operations, using timing signals to latch a first wordline for a first operation and then relinquish the X decode path so that a second operation can load an address and access a second wordline in another bank of the memory.
U.S. Pat. No. 6,501,700 to Pascucci describes an internal addressing structure for semiconductor memories having at least two memory banks. Here, each bank has its own row and column select circuitry. Each bank also includes an associated memory scan and address counter circuit for generating sequences of addressing codes for the corresponding bank. This structure permits sequential accessing of consecutive locations in alternating banks in an interleaved manner that is transparent to the external system.
In memory devices of the type having a plurality of banks or blocks of memory (hereinafter referred to as “planes”), each plane is effectively an independent entity having its own row and column decoders and capable of performing its own function (read, write, etc.) without interference from the other memory planes. Externally, the memory is seen as a single memory unit with a common address space, where one or more of the address bits designates a particular memory plane. Each plane may be further divided into sectors.
It is desirable to provide as much functional flexibility as possible to the memory device. The planes themselves provide some flexibility by allowing different planes to simultaneously carry out different functions. For example, it is possible for programming or erasing operation (both rather time consuming operations) to be performed in one plane, while read access to the other planes remains available. Read operations may be provided in both random access and burst modes.
An object of the present invention is to further enhance the functional flexibility of multi-plane memory devices, by providing for nested operations in the same plane, in addition to a variety of functions in the different planes.